Usage of Arrays at Vhdl
Hi everyone, At my this post we will learn how to define and use arrays. I created an array that has 4 elements and they are 6bits long individually.library ieee; use ieee.std_logic_1164.all; entity sonsonson is port( A : out std_logic_vector (5 downto 0); B : out std_logic_vector (5 downto 0); C : out std_logic_vector (5 downto 0); D : out std_logic_vector (5 downto 0)); end sonsonson; architecture behavior of sonsonson is type mydata is array (0 to 3) of std_logic_vector (5 downto 0); signal gokhan : mydata; begin gokhan(0) <="111111"; gokhan(1) <="111000"; gokhan(2) <="000111"; gokhan(3) <="110011"; A <= gokhan(0); B <= gokhan(1); C <= gokhan(2); D <= gokhan(3); --ozturkgokhan.com end behavior;Modelsim Output
Best Wishes, Gökhan Öztürk
Mart 15, 2016 tarihinde diğer, Vhdl içinde yayınlandı ve Fpga, Modelsim, Quartus, Vhdl olarak etiketlendi. Kalıcı bağlantıyı yer imlerinize ekleyin. Yorum yapın.
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