Hi everyone,

Today i made 2 bit upcounter. It counts from "00" to "11". 
Also i have an reset input. The meaning of the synchronous reset is that 
reset comes after the clock sense at the process.

As you might see from the modelsim output figure when 
reset occurs output become "00". 


 library ieee;
use ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;

entity gokhan1 is
port ( clk : in std_logic;
         rest: in std_logic;
         Q : out std_logic_vector(1 downto 0));
end gokhan1;

architecture behavioral of gokhan1 is
signal last: std_logic_vector (1 downto 0);

begin
    process(clk)
    begin
    if rest ='1' then 
        last <= "00";
        -- or you can use Q <= (1=>'0',0=>'0');
        -- or Q<= (others =>'0');
            elsif rising_edge(clk) then
            last <= last+1;
            else 
            last <= last;
    end if;
    end process;
    Q <= last;
--ozturkgokhan.com
end behavioral; 

Modelsim Output
Best Wishes,
gökhan öztürk

        
    
			

			
			
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