Implementation of State Machine in Vhdl
Hi everyone, Today i will show you how to create a state machine and implementation of that. Most important thing in designing at state machine is that lines.
type state_type is (zero, one, two, three, four, five, six, seven, eight, nine); signal state : state_type;
My state are from zero to nine.
After the implementing this code you can get the state diagram.
library ieee; use ieee.std_logic_1164.all; entity BCD_counter is generic(N : integer := 4); port ( clk : in std_logic; reset : in std_logic; y : inout std_logic_vector((N-1) downto 0); segment1: out std_logic_vector (6 downto 0) ); end entity; architecture bevahioral of BCD_counter is type state_type is (zero, one, two, three, four, five, six, seven, eight, nine); signal state : state_type; signal temp : std_logic_vector ((N-1) downto 0); begin process (clk, reset) begin if reset = '1' then state <= zero ; temp <= "0000"; elsif (rising_edge(clk)) then case state is when zero => temp <= "0000"; state <= one; when one => temp <= "0001"; state <= two; when two => temp <= "0010"; state <= three; when three => temp <= "0011"; state <=four ; when four => temp <= "0100"; state <=five ; when five => temp <= "0101"; state <=six ; when six => temp <= "0110"; state <=seven ; when seven => temp <= "0111"; state <=eight ; when eight => temp <= "1000"; state <=nine ; when others => temp <="1001"; state <=zero ; end case; end if; end process; y <= temp; process(y) begin case y is when "0000" => segment1 <= "1000000"; when "0001" => segment1 <= "1001111"; when "0010" => segment1 <= "0100100"; when "0011" => segment1 <= "0110000"; when "0100" => segment1 <= "0011001"; when "0101" => segment1 <= "0100100"; when "0110" => segment1 <= "0000010"; when "0111" => segment1 <= "0111000"; when "1000" => segment1 <= "0000000"; when "1001" => segment1 <= "0011000"; when "1010" => segment1 <= "0100000"; when "1011" => segment1 <= "0000011"; when "1100" => segment1 <= "1000110"; when "1101" => segment1 <= "0100001"; when "1110" => segment1 <= "0000110"; when others => segment1 <= "0001110"; end case; end process; end bevahioral; --ozturkgokhan.com
After implementing the code use this path to get state machine diagram “Tools>Netlist Viewers> State Machine Viewer”

State Machine Diagram

Modelsim Output
best wishes,
gökhan öztürk
Mart 24, 2016 tarihinde Vhdl içinde yayınlandı ve Altera, DIY, Fpga, Modelsim, programming, Quartus, Vhdl olarak etiketlendi. Kalıcı bağlantıyı yer imlerinize ekleyin. Yorum yapın.
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