Sequence Detector in Vhdl
Hi, As the improved version of my last post, Sequential Detector has states. Difference of this one is it has output called as "q". The states goes through zero to three. When the input is "1" and clock comes three times it reaches the state 'three' then it makes the output as "1". If the input still "1" when new clocks arise, output keeps as same. After that if we change the input "d" from "1" to "0" state changes to "zero" and output become "0". You can see the pattern at below.

Sequence Pattern
library ieee; use ieee.std_logic_1164.all; entity string_detector is port ( clk : in std_logic; d : in std_logic; rst : in std_logic; q : out std_logic:='0'); end entity; architecture behavioral of string_detector is type state_type is (zero, one, two, three); signal state : state_type; begin process (clk) begin if (rising_edge(clk)) then if rst = '1' then state <= zero; q <= '0'; else case state is when zero=> if d = '0' then state <= zero; elsif d='1' then state <= one; end if; when one=> if d = '0' then state <= zero; elsif d='1' then state <= two; end if; when two=> if d = '0' then state <= zero; elsif d='1' then state <= three; q <= '1'; end if; when three=> if d = '0' then state <= zero; q <= '0'; elsif d='1' then state <= three; end if; end case; end if; end if; end process; end behavioral; --ozturkgokhan.comModelsim Output
best wishes gökhan öztürk
Mart 30, 2016 tarihinde Vhdl içinde yayınlandı ve Altera, DIY, Fpga, Modelsim, Quartus, Vhdl olarak etiketlendi. Kalıcı bağlantıyı yer imlerinize ekleyin. Yorum yapın.
Yorum yapın
Comments 0