An Arithmetic Logic Unit (ALU) Design in VHDL

Hi Everyone,

At my this post i will try to build an arithmetic logic unit (ALU). ALU is a programmed or electronics circuit that makes user-defined arithmetic or logic tasks. I designed this ALU for my school homework.

My user-defined processes as at the given table.

An arithmetic logic unit (ALU)

An Arithmetic Logic Unit Processes

At the program, i have two times 3 bits long inputs (6 bits totally). When the inputs are given, we choose the operation by “sel” bits. Then operation will be processed. “Y” is  my output, i took that output and send them to segment1 and segment2 outputs. These are for seven-segment display output. By the help of these segment you can see result

 

library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use ieee.std_logic_unsigned.all;

entity ALU is

generic (width_data : integer :=4);

port(   a : in std_logic_vector  ( (width_data-2)  downto 0);
b : in std_logic_vector  ( (width_data-2)  downto 0);
sel : in std_logic_vector( (width_data-1)  downto 0);
y : inout std_logic_vector ( (2*width_data-1) downto 0);
segment1: out unsigned (6 downto 0);
segment2: out unsigned (6 downto 0)    );
end ALU;

architecture behavioral of ALU is
signal result : std_logic_vector((2*width_data-1) downto 0);
signal result1 : std_logic_vector((2*width_data-1) downto 0);
signal result2 : std_logic_vector((width_data-2) downto 0);

signal ax : std_logic_vector((2*width_data-1) downto 0):= "00000" & a ;
signal bx : std_logic_vector((2*width_data-1) downto 0):= "00000" & b;

begin

process (sel,a,b)
begin
case sel is
--sel(3) is 0
when "0000" => result <= ax ;
when "0001" => result <= ax + "001" ;
when "0010" => result <= ax - "001";
when "0011" => result <= bx;
when "0100" => result <= ax + bx;
when "0101" => result <= ax - bx;
when "0110" => result <= "00" & (a * b);
when "0111" => result <= "00000000";
--sel(3) is 1
when "1000" => result2 <= not a ;
when "1001" => result2 <= not b;
when "1010" => result2 <= a and b;
when "1011" => result2 <= a or b;
when "1100" => result2 <= a nand b;
when "1101" => result2 <= a nor b;
when "1110" => result2 <= a xor b;
when "1111" => result2 <= a xnor b;
end case;
end process;
result1 <= "00000" & result2;
y <= result when (sel(3)='0') else result1;

process(y)
begin
case y(3 downto 0) is
when "0000" => segment1 <= "1000000";
when "0001" => segment1 <= "1001111";
when "0010" => segment1 <= "0100100";
when "0011" => segment1 <= "0110000";
when "0100" => segment1 <= "0011001";
when "0101" => segment1 <= "0100100";
when "0110" => segment1 <= "0000010";
when "0111" => segment1 <= "0111000";
when "1000" => segment1 <= "0000000";
when "1001" => segment1 <= "0011000";
when "1010" => segment1 <= "0100000";
when "1011" => segment1 <= "0000011";
when "1100" => segment1 <= "1000110";
when "1101" => segment1 <= "0100001";
when "1110" => segment1 <= "0000110";
when others => segment1 <= "0001110";
end case;

case y(7 downto 4) is
when "0000" => segment2 <= "1000000";
when "0001" => segment2 <= "1001111";
when "0010" => segment2 <= "0100100";
when "0011" => segment2 <= "0110000";
when "0100" => segment2 <= "0011001";
when "0101" => segment2 <= "0100100";
when "0110" => segment2 <= "0000010";
when "0111" => segment2 <= "0111000";
when "1000" => segment2 <= "0000000";
when "1001" => segment2 <= "0011000";
when "1010" => segment2 <= "0100000";
when "1011" => segment2 <= "0000011";
when "1100" => segment2 <= "1000110";
when "1101" => segment2 <= "0100001";
when "1110" => segment2 <= "0000110";
when others => segment2 <= "0001110";
end case;

end process;
end behavioral;
--ozturkgokhan.com

Best wishes,

gökhan öztürk

Reklamlar

ozturkgokhan hakkında

Electrical and electronics engineer. In turkey.

Mayıs 4, 2016 tarihinde Vhdl içinde yayınlandı ve , , , , , , , , , , olarak etiketlendi. Kalıcı bağlantıyı yer imlerinize ekleyin. Yorum yapın.

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