Yazar arşivleri: ozturkgokhan
Hi everyone, today i will show you how to merge the st_logic bits and differecences between 0 to n and n down to 0.
library ieee; use ieee.std_logic_1164.all; entity ozturkgokhan is port( a : out std_logic_vector(7 downto 0); b : out std_logic_vector(7 downto 0); c : out std_logic_vector(0 to 7); d : out std_logic_vector(7 downto 0)); end ozturkgokhan; architecture behavioral of ozturkgokhan is signal gokhan :std_logic_vector (7 downto 0):="11110000"; signal gokhan1 :std_logic_vector (0 to 7) :="11110000"; begin -- merging values a <= gokhan(1 downto 0) & gokhan(7 downto 4) & gokhan(3 downto 2); --differecnce between 0 to 7 and 7 downto 0 b <= gokhan; c <= gokhan; d <= gokhan1; end behavioral; --ozturkgokhan.com
best wishes, gökhan öztürk
Hi everyone, Today i made 2 bit upcounter. It counts from "00" to "11". Also i have an reset input. The meaning of the synchronous reset is that reset comes after the clock sense at the process.
As you might see from the modelsim output figure when reset occurs output become "00".library ieee; use ieee.std_logic_1164.all; USE ieee.std_logic_unsigned.all; entity gokhan1 is port ( clk : in std_logic; rest: in std_logic; Q : out std_logic_vector(1 downto 0)); end gokhan1; architecture behavioral of gokhan1 is signal last: std_logic_vector (1 downto 0); begin process(clk) begin if rest ='1' then last <= "00"; -- or you can use Q <= (1=>'0',0=>'0'); -- or Q<= (others =>'0'); elsif rising_edge(clk) then last <= last+1; else last <= last; end if; end process; Q <= last; --ozturkgokhan.com end behavioral;
Hi everyone, At my this post we will learn how to define and use arrays. I created an array that has 4 elements and they are 6bits long individually.library ieee; use ieee.std_logic_1164.all; entity sonsonson is port( A : out std_logic_vector (5 downto 0); B : out std_logic_vector (5 downto 0); C : out std_logic_vector (5 downto 0); D : out std_logic_vector (5 downto 0)); end sonsonson; architecture behavior of sonsonson is type mydata is array (0 to 3) of std_logic_vector (5 downto 0); signal gokhan : mydata; begin gokhan(0) <="111111"; gokhan(1) <="111000"; gokhan(2) <="000111"; gokhan(3) <="110011"; A <= gokhan(0); B <= gokhan(1); C <= gokhan(2); D <= gokhan(3); --ozturkgokhan.com end behavior;Best Wishes, Gökhan Öztürk
This is my second post about Vhdl programming on Quartus II and Modelsim. I was searching how to converting a hex number to the bcd (binary coded decimal). Finally i found from web and learned.
As you see will see from the program, we define 8 bit long vector. And program converts a given hex number to bcd. I made two examples and showed at Modelsim.
library ieee; use ieee.std_logic_1164.ALL; use ieee.std_logic_arith.ALL; entity gokhan IS port( D : OUT STD_LOGIC_VECTOR(7 DOWNTO 0)); end gokhan; architecture behavior OF gokhan is begin D <= x"8A"; end behavior; --ozturkgokhan.com
Have a nice day, Gökhan Öztürk