# Kategori arşivi: Vhdl

## Usage of Arrays at Vhdl

Hi everyone, At my this post we will learn how to define and use arrays. I created an array that has 4 elements and they are 6bits long individually.library ieee; use ieee.std_logic_1164.all; entity sonsonson is port( A : out std_logic_vector (5 downto 0); B : out std_logic_vector (5 downto 0); C : out std_logic_vector (5 downto 0); D : out std_logic_vector (5 downto 0)); end sonsonson; architecture behavior of sonsonson is type mydata is array (0 to 3) of std_logic_vector (5 downto 0); signal gokhan : mydata; begin gokhan(0) <="111111"; gokhan(1) <="111000"; gokhan(2) <="000111"; gokhan(3) <="110011"; A <= gokhan(0); B <= gokhan(1); C <= gokhan(2); D <= gokhan(3); --ozturkgokhan.com end behavior;Best Wishes, Gökhan Öztürk

## Converting a Hexadecimal Value to BCD in Vhdl

Hi everyone,

This is my second post about Vhdl programming on Quartus II and Modelsim. I was searching how to converting a hex number to the bcd (binary coded decimal). Finally i found from web and learned.

As you see will see from the program, we define 8 bit long vector. And program converts a given hex number to bcd. I made two examples and showed at Modelsim.

library ieee; use ieee.std_logic_1164.ALL; use ieee.std_logic_arith.ALL; entity gokhan IS port( D : OUT STD_LOGIC_VECTOR(7 DOWNTO 0)); end gokhan; architecture behavior OF gokhan is begin D <= x"8A"; end behavior; --ozturkgokhan.com

Have a nice day, Gökhan Öztürk

## Vhdl Programming on Quartus II

Hi everyone,

At my this post i will open a new area to my workings. From today on, i started to work about VDHL(1) language and FPGA(2) demo board. I took e lesson about VHDL language two years ago. We used Xilinx’s(3) program. Then i refreshed my knowledge about basics of digital computing. From now on i will use Altera’s (4) “Altera Quartus II”.

If u have no idea about usage of Quartus 2 and Modelsim just watch this video (5). This guys recounts well and it is gonna help you.

I designed this program to make the basic logic operations.

library ieee; use ieee.std_logic_1164.all; entity example is port ( A : in std_logic_vector (1 downto 0); B : out std_logic_vector (3 downto 0)); end example; architecture behavior of example is begin B(0) <= A(0) or A(1); B(1) <= A(0) and A(1); B(2) <= A(0) xor A(1); B(3) <= A(0) nand A(1); end behavior; --ozturkgokhan.com

Let us examine the output of program.

As you see A(0)=0, A(1)=1. By the varying yellow line you can see results of outputs at second column. B(0) is the output of or gate. '0' or '1' equals 1. B(1) is the output of and gate. '0' and '1' equals 0 B(2) is the output of xor gate. '0' xor'1' equals 1 B(3) is the output of nand gate. '0' nand '1' equals 1

Have a nice day, Gökhan Öztürk (1) https://en.wikipedia.org/wiki/VHDL (2) https://en.wikipedia.org/wiki/Field-programmable_gate_array (3) https://en.wikipedia.org/wiki/Xilinx (4) https://en.wikipedia.org/wiki/Altera (5) https://www.youtube.com/watch?v=9xr9ARUDxz4