Blog Arşivleri

Start-Stop Counter at App Inventor2

Mar 31

Yazan:

Hi,

At my this post, i will continue to use App inventor 2. This is the first time of using  app inventor2 since it is updated at 28 Feb.

My aim is making a downcounter that counts from a number that is entered from the screen. Then it starts downcounting when we press start button. If i press to stop, it freezes at that current number. After that we press to start again, it continues to count from the last number until it arrives to zero or stopping again.

Ekran Alıntısı2

Designer Window

Ekran Alıntısı

Block Programming Window

Screenshot_2016-03-31-17-15-10

Emulator Screen -1-

Screenshot_2016-03-31-17-15-23

Emulator Screeen -2-

Best wishes,

gökhan öztürk

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BCD Upcounter with Seven Segment display

Mar 23

Yazan: 

Hi everyone,
today we will learn how to use seven segment display and usage of case-when. 
At my one of the earlier post i did counter but now i improved the program. 
Now it counts from "0000" to "1001" then it goes back.

I have a reset input as you see and at the end of the program there are two when-case 
situation. These are fır the seven segment displays at Cyclone V SoC 5CSEMA5F31 board.
library ieee;
use ieee.std_logic_1164.all;
use IEEE.STD_LOGIC_ARITH.ALL;
use ieee.std_logic_unsigned.all;

entity BCD_counter is
generic (N : integer:= 3 );
port( clk : in std_logic;
rst : in std_logic;
y   : out std_logic_vector(3 downto 0) );
end entity;

architecture behavioral of BCD_counter is

signal ara : std_logic_vector(3 downto 0);

begin

process(clk,rst)

begin
if rst = '1' then
ara <= "0000";
--    elsif ara = "1010" then
--    ara <= "0000";
elsif rising_edge(clk) then
ara <= ara + "0001" ;
else
ara <= ara;
end if;
end process;
y <= ara;
process(y)
begin
case y(3 downto 0) is
when "0000" => segment1 <= "1000000";
when "0001" => segment1 <= "1001111";
when "0010" => segment1 <= "0100100";
when "0011" => segment1 <= "0110000";
when "0100" => segment1 <= "0011001";
when "0101" => segment1 <= "0100100";
when "0110" => segment1 <= "0000010";
when "0111" => segment1 <= "0111000";
when "1000" => segment1 <= "0000000";
when "1001" => segment1 <= "0011000";
when "1010" => segment1 <= "0100000";
when "1011" => segment1 <= "0000011";
when "1100" => segment1 <= "1000110";
when "1101" => segment1 <= "0100001";
when "1110" => segment1 <= "0000110";
when others => segment1 <= "0001110";
end case;

case y(7 downto 4) is
when "0000" => segment2 <= "1000000";
when "0001" => segment2 <= "1001111";
when "0010" => segment2 <= "0100100";
when "0011" => segment2 <= "0110000";
when "0100" => segment2 <= "0011001";
when "0101" => segment2 <= "0100100";
when "0110" => segment2 <= "0000010";
when "0111" => segment2 <= "0111000";
when "1000" => segment2 <= "0000000";
when "1001" => segment2 <= "0011000";
when "1010" => segment2 <= "0100000";
when "1011" => segment2 <= "0000011";
when "1100" => segment2 <= "1000110";
when "1101" => segment2 <= "0100001";
when "1110" => segment2 <= "0000110";
when others => segment2 <= "0001110";
end case;

end process;
end behavioral;
--ozturkgokhan.com
s1

Modelsim Output

best wishes,
gökhan öztürk

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Converting a Hexadecimal Value to BCD in Vhdl

Mar 14

Yazan:

Hi everyone,

This is my second post about Vhdl programming on Quartus II and Modelsim. I was searching how to converting a hex number to the bcd (binary coded decimal). Finally i found from web and learned.

As you see will see from the program, we define 8 bit long vector. And program converts a given hex number to bcd. I made two examples and showed at Modelsim.


library ieee;
use ieee.std_logic_1164.ALL;
use ieee.std_logic_arith.ALL;

entity gokhan IS
port(
D : OUT STD_LOGIC_VECTOR(7 DOWNTO 0));
end gokhan;

architecture behavior OF gokhan is

begin
D <= x"8A";

end behavior;
--ozturkgokhan.com
output of fc2

Expected value of FC hex

output of fc

Simulation result of output FC hex

output of fc4

Expected value of 8A hex



output of fc3
Simulation result of output 8A Hex


Have a nice day,
Gökhan Öztürk

			


			

			

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Vhdl Programming on Quartus II
	
	

		
Mar 10

	


	

		
Yazan: 

	


	

		
Hi everyone,


At my this post i will open a new area to my workings. From today on, i started to work about VDHL(1) language and FPGA(2) demo board. I took e lesson about VHDL language two years ago. We used Xilinx’s(3) program.  Then i refreshed my  knowledge about basics of digital computing. From now on  i will use Altera’s (4) “Altera Quartus II”.


If u have no idea about usage of Quartus 2 and Modelsim just watch this video (5). This guys  recounts well and it is gonna help you.


I designed this program to  make the basic logic operations.


library ieee;
use ieee.std_logic_1164.all;

entity example is
port ( A :  in std_logic_vector (1 downto 0);
B :  out std_logic_vector (3 downto 0));
end example;

architecture behavior of example is

begin
B(0) <= A(0) or A(1);
B(1) <= A(0) and A(1);
B(2) <= A(0) xor A(1);
B(3) <= A(0) nand A(1);

end behavior;

--ozturkgokhan.com



Let us examine the output of program.


Ekran Alıntısı
Modelsim Output


As you see A(0)=0, A(1)=1. By the varying yellow line you can see results of outputs 
at second column.

B(0) is the output of or gate.   '0' or '1' equals 1.
B(1) is the output of and gate.  '0' and '1' equals 0
B(2) is the output of xor gate.  '0' xor'1' equals 1
B(3) is the output of nand gate. '0' nand '1' equals 1


Have a nice day,
Gökhan Öztürk

(1) https://en.wikipedia.org/wiki/VHDL
(2) https://en.wikipedia.org/wiki/Field-programmable_gate_array
(3) https://en.wikipedia.org/wiki/Xilinx
(4) https://en.wikipedia.org/wiki/Altera
(5) https://www.youtube.com/watch?v=9xr9ARUDxz4

			


			

			

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