Hi everyone, Today i made 2 bit upcounter. It counts from "00" to "11". Also i have an reset input. The meaning of the synchronous reset is that reset comes after the clock sense at the process.
As you might see from the modelsim output figure when reset occurs output become "00".library ieee; use ieee.std_logic_1164.all; USE ieee.std_logic_unsigned.all; entity gokhan1 is port ( clk : in std_logic; rest: in std_logic; Q : out std_logic_vector(1 downto 0)); end gokhan1; architecture behavioral of gokhan1 is signal last: std_logic_vector (1 downto 0); begin process(clk) begin if rest ='1' then last <= "00"; -- or you can use Q <= (1=>'0',0=>'0'); -- or Q<= (others =>'0'); elsif rising_edge(clk) then last <= last+1; else last <= last; end if; end process; Q <= last; --ozturkgokhan.com end behavioral;
This is my second post about Vhdl programming on Quartus II and Modelsim. I was searching how to converting a hex number to the bcd (binary coded decimal). Finally i found from web and learned.
As you see will see from the program, we define 8 bit long vector. And program converts a given hex number to bcd. I made two examples and showed at Modelsim.
library ieee; use ieee.std_logic_1164.ALL; use ieee.std_logic_arith.ALL; entity gokhan IS port( D : OUT STD_LOGIC_VECTOR(7 DOWNTO 0)); end gokhan; architecture behavior OF gokhan is begin D <= x"8A"; end behavior; --ozturkgokhan.com
Have a nice day, Gökhan Öztürk
At my this post i will open a new area to my workings. From today on, i started to work about VDHL(1) language and FPGA(2) demo board. I took e lesson about VHDL language two years ago. We used Xilinx’s(3) program. Then i refreshed my knowledge about basics of digital computing. From now on i will use Altera’s (4) “Altera Quartus II”.
If u have no idea about usage of Quartus 2 and Modelsim just watch this video (5). This guys recounts well and it is gonna help you.
I designed this program to make the basic logic operations.
library ieee; use ieee.std_logic_1164.all; entity example is port ( A : in std_logic_vector (1 downto 0); B : out std_logic_vector (3 downto 0)); end example; architecture behavior of example is begin B(0) <= A(0) or A(1); B(1) <= A(0) and A(1); B(2) <= A(0) xor A(1); B(3) <= A(0) nand A(1); end behavior; --ozturkgokhan.com
Let us examine the output of program.
As you see A(0)=0, A(1)=1. By the varying yellow line you can see results of outputs at second column. B(0) is the output of or gate. '0' or '1' equals 1. B(1) is the output of and gate. '0' and '1' equals 0 B(2) is the output of xor gate. '0' xor'1' equals 1 B(3) is the output of nand gate. '0' nand '1' equals 1
Have a nice day, Gökhan Öztürk (1) https://en.wikipedia.org/wiki/VHDL (2) https://en.wikipedia.org/wiki/Field-programmable_gate_array (3) https://en.wikipedia.org/wiki/Xilinx (4) https://en.wikipedia.org/wiki/Altera (5) https://www.youtube.com/watch?v=9xr9ARUDxz4
Now i will try to make downcounter at app inventor2.
At my first post about app inventor, i made button control.
In this application we will use it and we will create a downcounter.
We will use clock, button and label component.
When we push the start button, a counter will start to count from ten to zero..
I defined a variable named “value1” that has the value of ten. At the beginning -when screeen initialized- clock is disabled. When we push the button, value of the “value1” will decrease one-by-one until it reaches to zero. When the counter’s value is zero, button’s text will change to “finished”. Then it will wait for another input as pushing.