Blog Arşivleri

An Arithmetic Logic Unit (ALU) Design in VHDL

Hi Everyone,

At my this post i will try to build an arithmetic logic unit (ALU). ALU is a programmed or electronics circuit that makes user-defined arithmetic or logic tasks. I designed this ALU for my school homework.

My user-defined processes as at the given table.

An arithmetic logic unit (ALU)

An Arithmetic Logic Unit Processes

At the program, i have two times 3 bits long inputs (6 bits totally). When the inputs are given, we choose the operation by “sel” bits. Then operation will be processed. “Y” is  my output, i took that output and send them to segment1 and segment2 outputs. These are for seven-segment display output. By the help of these segment you can see result

 

library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use ieee.std_logic_unsigned.all;

entity ALU is

generic (width_data : integer :=4);

port(   a : in std_logic_vector  ( (width_data-2)  downto 0);
b : in std_logic_vector  ( (width_data-2)  downto 0);
sel : in std_logic_vector( (width_data-1)  downto 0);
y : inout std_logic_vector ( (2*width_data-1) downto 0);
segment1: out unsigned (6 downto 0);
segment2: out unsigned (6 downto 0)    );
end ALU;

architecture behavioral of ALU is
signal result : std_logic_vector((2*width_data-1) downto 0);
signal result1 : std_logic_vector((2*width_data-1) downto 0);
signal result2 : std_logic_vector((width_data-2) downto 0);

signal ax : std_logic_vector((2*width_data-1) downto 0):= "00000" & a ;
signal bx : std_logic_vector((2*width_data-1) downto 0):= "00000" & b;

begin

process (sel,a,b)
begin
case sel is
--sel(3) is 0
when "0000" => result <= ax ;
when "0001" => result <= ax + "001" ;
when "0010" => result <= ax - "001";
when "0011" => result <= bx;
when "0100" => result <= ax + bx;
when "0101" => result <= ax - bx;
when "0110" => result <= "00" & (a * b);
when "0111" => result <= "00000000";
--sel(3) is 1
when "1000" => result2 <= not a ;
when "1001" => result2 <= not b;
when "1010" => result2 <= a and b;
when "1011" => result2 <= a or b;
when "1100" => result2 <= a nand b;
when "1101" => result2 <= a nor b;
when "1110" => result2 <= a xor b;
when "1111" => result2 <= a xnor b;
end case;
end process;
result1 <= "00000" & result2;
y <= result when (sel(3)='0') else result1;

process(y)
begin
case y(3 downto 0) is
when "0000" => segment1 <= "1000000";
when "0001" => segment1 <= "1001111";
when "0010" => segment1 <= "0100100";
when "0011" => segment1 <= "0110000";
when "0100" => segment1 <= "0011001";
when "0101" => segment1 <= "0100100";
when "0110" => segment1 <= "0000010";
when "0111" => segment1 <= "0111000";
when "1000" => segment1 <= "0000000";
when "1001" => segment1 <= "0011000";
when "1010" => segment1 <= "0100000";
when "1011" => segment1 <= "0000011";
when "1100" => segment1 <= "1000110";
when "1101" => segment1 <= "0100001";
when "1110" => segment1 <= "0000110";
when others => segment1 <= "0001110";
end case;

case y(7 downto 4) is
when "0000" => segment2 <= "1000000";
when "0001" => segment2 <= "1001111";
when "0010" => segment2 <= "0100100";
when "0011" => segment2 <= "0110000";
when "0100" => segment2 <= "0011001";
when "0101" => segment2 <= "0100100";
when "0110" => segment2 <= "0000010";
when "0111" => segment2 <= "0111000";
when "1000" => segment2 <= "0000000";
when "1001" => segment2 <= "0011000";
when "1010" => segment2 <= "0100000";
when "1011" => segment2 <= "0000011";
when "1100" => segment2 <= "1000110";
when "1101" => segment2 <= "0100001";
when "1110" => segment2 <= "0000110";
when others => segment2 <= "0001110";
end case;

end process;
end behavioral;
--ozturkgokhan.com

Best wishes,

gökhan öztürk

Reklamlar

Converting a Hexadecimal Value to BCD in Vhdl

Hi everyone,

This is my second post about Vhdl programming on Quartus II and Modelsim. I was searching how to converting a hex number to the bcd (binary coded decimal). Finally i found from web and learned.

As you see will see from the program, we define 8 bit long vector. And program converts a given hex number to bcd. I made two examples and showed at Modelsim.


library ieee;
use ieee.std_logic_1164.ALL;
use ieee.std_logic_arith.ALL;

entity gokhan IS
port(
D : OUT STD_LOGIC_VECTOR(7 DOWNTO 0));
end gokhan;

architecture behavior OF gokhan is

begin
D <= x"8A";

end behavior;
--ozturkgokhan.com

output of fc2

Expected value of FC hex

output of fc

Simulation result of output FC hex

output of fc4

Expected value of 8A hex


output of fc3

Simulation result of output 8A Hex

Have a nice day,
Gökhan Öztürk

Making Downcounter at App Inventor 2

Hi everybody,
Now i will try to make downcounter at app inventor2.
At my first post  about app inventor, i made button control.
In this application we will use it and we will create a downcounter.

We will use clock, button and label component.

design

When we push the start button, a counter will start to count from ten to zero..

block

I defined a variable named “value1” that has the value of ten. At the beginning -when screeen initialized- clock is disabled. When we push the button, value of the “value1” will decrease one-by-one until it reaches to zero. When the counter’s value is zero, button’s text will change to “finished”. Then it will wait for another input as pushing.

Best Wishes,

Gökhan Öztürk

Usage of Slider Component at App Inventor 2

Hi, my second post will be about usage of slide component at app inventor 2.

Slider is a component that its value change by the position. We can define the max. and min. value.

I took a label and slider from user interface and put them in to a VerticalArrangement that taken from layout.

design

When we change the slide its value will change and then label will change. If the thumb position is lower than 25 label will be “b” and if the thumb position is higher than 25 label will be “a”

blocks

Program output at screen.

gokhan

best wishes,

gökhan öztürk