Blog Arşivleri

Sequence Detector in Vhdl

Hi,
As the improved version of my last post, Sequential Detector has states. 
Difference of this one is it has output called  as "q". The states goes 
through zero to three. When the input is "1" and clock comes three times
it reaches the state 'three' then it makes the output as "1". If the input
still "1" when new clocks arise, output keeps as same. After that if we 
change the input "d" from "1" to "0" state changes to "zero" and output 
become "0". You can see the pattern at below.

sequencedetection

Sequence Pattern


library ieee;
use ieee.std_logic_1164.all;
entity string_detector is
    port
    (
        clk         : in    std_logic;
        d          : in    std_logic;
        rst        : in    std_logic;
        q           : out std_logic:='0');
end entity;

architecture behavioral of string_detector is

    type state_type is (zero, one, two, three);
    signal state : state_type;

begin

    process (clk)
    begin

    if (rising_edge(clk)) then
        if rst = '1' then
            state <= zero;
                    q <= '0'; 
        else

            case state is

                when zero=>
                    if d = '0' then
                        state <= zero;
                    elsif d='1' then
                        state <= one;
                    end if;

                when one=>
                    if d = '0' then
                        state <= zero;
                    elsif d='1' then
                        state <= two;
                    end if;

                when two=>
                    if d = '0' then
                        state <= zero;
                    elsif d='1' then
                        state <= three;
                             q <= '1';
                    end if;

                when three=>
                    if d = '0' then
                        state <= zero;
                                q <= '0';
                    elsif d='1' then
                        state <= three;
                    end if;

            end case;

        end if;
        end if;
    end process;

end behavioral;
--ozturkgokhan.com
modelsim output

Modelsim Output

best wishes
gökhan öztürk

Implementation of State Machine in Vhdl

Hi everyone,

Today i will show you how to create a state machine and implementation of that. 
Most important thing in designing at state machine is that lines.
type state_type is (zero, one, two, three, four, five, six, seven, eight, nine);
signal state : state_type;

My state are from zero to nine.
After the implementing this code you can get the state diagram.

library ieee;
use ieee.std_logic_1164.all;

entity BCD_counter is
generic(N : integer := 4);
port
(
clk         : in    std_logic;
reset        : in    std_logic;
y     : inout std_logic_vector((N-1) downto 0);
segment1: out std_logic_vector (6 downto 0)    );

end entity;

architecture bevahioral of BCD_counter is

type state_type is (zero, one, two, three, four, five, six, seven, eight, nine);
signal state : state_type;
signal temp : std_logic_vector ((N-1) downto 0);

begin

process (clk, reset)
begin

if reset = '1' then
state <= zero ;
temp <= "0000";

elsif (rising_edge(clk)) then

case state is

when zero =>
temp <= "0000";
state <= one;

when one =>
temp <= "0001";
state <= two;

when two =>
temp <= "0010";
state <= three;

when three =>
temp <= "0011";
state <=four ;

when four =>
temp <= "0100";
state <=five ;

when five =>
temp <= "0101";
state <=six ;

when six =>
temp <= "0110";
state <=seven ;

when seven =>
temp <= "0111";
state <=eight ;

when eight =>
temp <= "1000";
state <=nine ;

when others =>
temp <="1001";
state <=zero ;

end case;

end if;
end process;

y <= temp;

process(y)
begin
case y is
when "0000" => segment1 <= "1000000";
when "0001" => segment1 <= "1001111";
when "0010" => segment1 <= "0100100";
when "0011" => segment1 <= "0110000";
when "0100" => segment1 <= "0011001";
when "0101" => segment1 <= "0100100";
when "0110" => segment1 <= "0000010";
when "0111" => segment1 <= "0111000";
when "1000" => segment1 <= "0000000";
when "1001" => segment1 <= "0011000";
when "1010" => segment1 <= "0100000";
when "1011" => segment1 <= "0000011";
when "1100" => segment1 <= "1000110";
when "1101" => segment1 <= "0100001";
when "1110" => segment1 <= "0000110";
when others => segment1 <= "0001110";
end case;

end process;

end bevahioral;
--ozturkgokhan.com

After implementing the code use this path to get state machine diagram “Tools>Netlist Viewers> State Machine Viewer”

BCD_counter_state

State Machine Diagram

 

sinyaller

Modelsim Output

best wishes,
gökhan öztürk

BCD Upcounter with Seven Segment display

Hi everyone,
today we will learn how to use seven segment display and usage of case-when. 
At my one of the earlier post i did counter but now i improved the program. 
Now it counts from "0000" to "1001" then it goes back.

I have a reset input as you see and at the end of the program there are two when-case 
situation. These are fır the seven segment displays at Cyclone V SoC 5CSEMA5F31 board.
library ieee;
use ieee.std_logic_1164.all;
use IEEE.STD_LOGIC_ARITH.ALL;
use ieee.std_logic_unsigned.all;

entity BCD_counter is
generic (N : integer:= 3 );
port( clk : in std_logic;
rst : in std_logic;
y   : out std_logic_vector(3 downto 0) );
end entity;

architecture behavioral of BCD_counter is

signal ara : std_logic_vector(3 downto 0);

begin

process(clk,rst)

begin
if rst = '1' then
ara <= "0000";
--    elsif ara = "1010" then
--    ara <= "0000";
elsif rising_edge(clk) then
ara <= ara + "0001" ;
else
ara <= ara;
end if;
end process;
y <= ara;
process(y)
begin
case y(3 downto 0) is
when "0000" => segment1 <= "1000000";
when "0001" => segment1 <= "1001111";
when "0010" => segment1 <= "0100100";
when "0011" => segment1 <= "0110000";
when "0100" => segment1 <= "0011001";
when "0101" => segment1 <= "0100100";
when "0110" => segment1 <= "0000010";
when "0111" => segment1 <= "0111000";
when "1000" => segment1 <= "0000000";
when "1001" => segment1 <= "0011000";
when "1010" => segment1 <= "0100000";
when "1011" => segment1 <= "0000011";
when "1100" => segment1 <= "1000110";
when "1101" => segment1 <= "0100001";
when "1110" => segment1 <= "0000110";
when others => segment1 <= "0001110";
end case;

case y(7 downto 4) is
when "0000" => segment2 <= "1000000";
when "0001" => segment2 <= "1001111";
when "0010" => segment2 <= "0100100";
when "0011" => segment2 <= "0110000";
when "0100" => segment2 <= "0011001";
when "0101" => segment2 <= "0100100";
when "0110" => segment2 <= "0000010";
when "0111" => segment2 <= "0111000";
when "1000" => segment2 <= "0000000";
when "1001" => segment2 <= "0011000";
when "1010" => segment2 <= "0100000";
when "1011" => segment2 <= "0000011";
when "1100" => segment2 <= "1000110";
when "1101" => segment2 <= "0100001";
when "1110" => segment2 <= "0000110";
when others => segment2 <= "0001110";
end case;

end process;
end behavioral;
--ozturkgokhan.com
s1

Modelsim Output

best wishes,
gökhan öztürk

Differences on std_logic in Vhdl

Hi everyone,
today i will show you how to merge the st_logic bits 
and differecences between 0 to n and n down to 0.
library ieee;
use ieee.std_logic_1164.all;

entity ozturkgokhan is
port( a : out std_logic_vector(7 downto 0);
b : out std_logic_vector(7 downto 0);
c : out std_logic_vector(0 to 7);
d : out std_logic_vector(7 downto 0));
end ozturkgokhan;

architecture behavioral of ozturkgokhan is
signal gokhan  :std_logic_vector (7 downto 0):="11110000";
signal gokhan1 :std_logic_vector (0 to 7)    :="11110000";

begin
-- merging values
a <= gokhan(1 downto 0) & gokhan(7 downto 4) & gokhan(3 downto 2);
--differecnce between 0 to 7 and 7 downto 0
b <= gokhan;
c <= gokhan;
d <= gokhan1;
end behavioral;
--ozturkgokhan.com
Ekran Alıntısı

Modelsim Output

best wishes,
gökhan öztürk