Blog Arşivleri

Two Bit Up Counter (With Synchronous Reset) at VHDL

Hi everyone,

Today i made 2 bit upcounter. It counts from "00" to "11". 
Also i have an reset input. The meaning of the synchronous reset is that 
reset comes after the clock sense at the process.
As you might see from the modelsim output figure when 
reset occurs output become "00". 

 library ieee;
use ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;

entity gokhan1 is
port ( clk : in std_logic;
         rest: in std_logic;
         Q : out std_logic_vector(1 downto 0));
end gokhan1;

architecture behavioral of gokhan1 is
signal last: std_logic_vector (1 downto 0);

    if rest ='1' then 
        last <= "00";
        -- or you can use Q <= (1=>'0',0=>'0');
        -- or Q<= (others =>'0');
            elsif rising_edge(clk) then
            last <= last+1;
            last <= last;
    end if;
    end process;
    Q <= last;
end behavioral; 

Modelsim Output

Best Wishes,

gökhan öztürk

Usage of Arrays at Vhdl

Hi everyone,

At my this post we will learn how to define and use arrays. 
I created an array that has 4 elements and they are 6bits long individually.

library ieee;
use ieee.std_logic_1164.all;

entity sonsonson is
A : out std_logic_vector (5 downto 0);
B : out std_logic_vector (5 downto 0);
C : out std_logic_vector (5 downto 0);
D : out std_logic_vector (5 downto 0));
end sonsonson;

architecture behavior of sonsonson is
type mydata is array (0 to 3) of std_logic_vector (5 downto 0);
signal gokhan : mydata;

gokhan(0) <="111111";
gokhan(1) <="111000";
gokhan(2) <="000111";
gokhan(3) <="110011"; 

A <= gokhan(0);
B <= gokhan(1);
C <= gokhan(2);
D <= gokhan(3);
end behavior;

Modelsim Output

Best Wishes,
Gökhan Öztürk

Vhdl Programming on Quartus II

Hi everyone,

At my this post i will open a new area to my workings. From today on, i started to work about VDHL(1) language and FPGA(2) demo board. I took e lesson about VHDL language two years ago. We used Xilinx’s(3) program.  Then i refreshed my  knowledge about basics of digital computing. From now on  i will use Altera’s (4) “Altera Quartus II”.

If u have no idea about usage of Quartus 2 and Modelsim just watch this video (5). This guys  recounts well and it is gonna help you.

I designed this program to  make the basic logic operations.

library ieee;
use ieee.std_logic_1164.all;

entity example is
port ( A :  in std_logic_vector (1 downto 0);
B :  out std_logic_vector (3 downto 0));
end example;

architecture behavior of example is

B(0) <= A(0) or A(1);
B(1) <= A(0) and A(1);
B(2) <= A(0) xor A(1);
B(3) <= A(0) nand A(1);

end behavior;

Let us examine the output of program.

Ekran Alıntısı

Modelsim Output

As you see A(0)=0, A(1)=1. By the varying yellow line you can see results of outputs 
at second column.

B(0) is the output of or gate.   '0' or '1' equals 1.
B(1) is the output of and gate.  '0' and '1' equals 0
B(2) is the output of xor gate.  '0' xor'1' equals 1
B(3) is the output of nand gate. '0' nand '1' equals 1
Have a nice day,
Gökhan Öztürk