Blog Arşivleri

Start-Stop Counter at App Inventor2

Hi,

At my this post, i will continue to use App inventor 2. This is the first time of using  app inventor2 since it is updated at 28 Feb.

My aim is making a downcounter that counts from a number that is entered from the screen. Then it starts downcounting when we press start button. If i press to stop, it freezes at that current number. After that we press to start again, it continues to count from the last number until it arrives to zero or stopping again.

Ekran Alıntısı2

Designer Window

Ekran Alıntısı

Block Programming Window

Screenshot_2016-03-31-17-15-10

Emulator Screen -1-

Screenshot_2016-03-31-17-15-23

Emulator Screeen -2-

Best wishes,

gökhan öztürk

Implementation of State Machine in Vhdl

Hi everyone,

Today i will show you how to create a state machine and implementation of that. 
Most important thing in designing at state machine is that lines.
type state_type is (zero, one, two, three, four, five, six, seven, eight, nine);
signal state : state_type;

My state are from zero to nine.
After the implementing this code you can get the state diagram.

library ieee;
use ieee.std_logic_1164.all;

entity BCD_counter is
generic(N : integer := 4);
port
(
clk         : in    std_logic;
reset        : in    std_logic;
y     : inout std_logic_vector((N-1) downto 0);
segment1: out std_logic_vector (6 downto 0)    );

end entity;

architecture bevahioral of BCD_counter is

type state_type is (zero, one, two, three, four, five, six, seven, eight, nine);
signal state : state_type;
signal temp : std_logic_vector ((N-1) downto 0);

begin

process (clk, reset)
begin

if reset = '1' then
state <= zero ;
temp <= "0000";

elsif (rising_edge(clk)) then

case state is

when zero =>
temp <= "0000";
state <= one;

when one =>
temp <= "0001";
state <= two;

when two =>
temp <= "0010";
state <= three;

when three =>
temp <= "0011";
state <=four ;

when four =>
temp <= "0100";
state <=five ;

when five =>
temp <= "0101";
state <=six ;

when six =>
temp <= "0110";
state <=seven ;

when seven =>
temp <= "0111";
state <=eight ;

when eight =>
temp <= "1000";
state <=nine ;

when others =>
temp <="1001";
state <=zero ;

end case;

end if;
end process;

y <= temp;

process(y)
begin
case y is
when "0000" => segment1 <= "1000000";
when "0001" => segment1 <= "1001111";
when "0010" => segment1 <= "0100100";
when "0011" => segment1 <= "0110000";
when "0100" => segment1 <= "0011001";
when "0101" => segment1 <= "0100100";
when "0110" => segment1 <= "0000010";
when "0111" => segment1 <= "0111000";
when "1000" => segment1 <= "0000000";
when "1001" => segment1 <= "0011000";
when "1010" => segment1 <= "0100000";
when "1011" => segment1 <= "0000011";
when "1100" => segment1 <= "1000110";
when "1101" => segment1 <= "0100001";
when "1110" => segment1 <= "0000110";
when others => segment1 <= "0001110";
end case;

end process;

end bevahioral;
--ozturkgokhan.com

After implementing the code use this path to get state machine diagram “Tools>Netlist Viewers> State Machine Viewer”

BCD_counter_state

State Machine Diagram

 

sinyaller

Modelsim Output

best wishes,
gökhan öztürk

BCD Upcounter with Seven Segment display

Hi everyone,
today we will learn how to use seven segment display and usage of case-when. 
At my one of the earlier post i did counter but now i improved the program. 
Now it counts from "0000" to "1001" then it goes back.

I have a reset input as you see and at the end of the program there are two when-case 
situation. These are fır the seven segment displays at Cyclone V SoC 5CSEMA5F31 board.
library ieee;
use ieee.std_logic_1164.all;
use IEEE.STD_LOGIC_ARITH.ALL;
use ieee.std_logic_unsigned.all;

entity BCD_counter is
generic (N : integer:= 3 );
port( clk : in std_logic;
rst : in std_logic;
y   : out std_logic_vector(3 downto 0) );
end entity;

architecture behavioral of BCD_counter is

signal ara : std_logic_vector(3 downto 0);

begin

process(clk,rst)

begin
if rst = '1' then
ara <= "0000";
--    elsif ara = "1010" then
--    ara <= "0000";
elsif rising_edge(clk) then
ara <= ara + "0001" ;
else
ara <= ara;
end if;
end process;
y <= ara;
process(y)
begin
case y(3 downto 0) is
when "0000" => segment1 <= "1000000";
when "0001" => segment1 <= "1001111";
when "0010" => segment1 <= "0100100";
when "0011" => segment1 <= "0110000";
when "0100" => segment1 <= "0011001";
when "0101" => segment1 <= "0100100";
when "0110" => segment1 <= "0000010";
when "0111" => segment1 <= "0111000";
when "1000" => segment1 <= "0000000";
when "1001" => segment1 <= "0011000";
when "1010" => segment1 <= "0100000";
when "1011" => segment1 <= "0000011";
when "1100" => segment1 <= "1000110";
when "1101" => segment1 <= "0100001";
when "1110" => segment1 <= "0000110";
when others => segment1 <= "0001110";
end case;

case y(7 downto 4) is
when "0000" => segment2 <= "1000000";
when "0001" => segment2 <= "1001111";
when "0010" => segment2 <= "0100100";
when "0011" => segment2 <= "0110000";
when "0100" => segment2 <= "0011001";
when "0101" => segment2 <= "0100100";
when "0110" => segment2 <= "0000010";
when "0111" => segment2 <= "0111000";
when "1000" => segment2 <= "0000000";
when "1001" => segment2 <= "0011000";
when "1010" => segment2 <= "0100000";
when "1011" => segment2 <= "0000011";
when "1100" => segment2 <= "1000110";
when "1101" => segment2 <= "0100001";
when "1110" => segment2 <= "0000110";
when others => segment2 <= "0001110";
end case;

end process;
end behavioral;
--ozturkgokhan.com
s1

Modelsim Output

best wishes,
gökhan öztürk

Converting a Hexadecimal Value to BCD in Vhdl

Hi everyone,

This is my second post about Vhdl programming on Quartus II and Modelsim. I was searching how to converting a hex number to the bcd (binary coded decimal). Finally i found from web and learned.

As you see will see from the program, we define 8 bit long vector. And program converts a given hex number to bcd. I made two examples and showed at Modelsim.


library ieee;
use ieee.std_logic_1164.ALL;
use ieee.std_logic_arith.ALL;

entity gokhan IS
port(
D : OUT STD_LOGIC_VECTOR(7 DOWNTO 0));
end gokhan;

architecture behavior OF gokhan is

begin
D <= x"8A";

end behavior;
--ozturkgokhan.com

output of fc2

Expected value of FC hex

output of fc

Simulation result of output FC hex

output of fc4

Expected value of 8A hex


output of fc3

Simulation result of output 8A Hex

Have a nice day,
Gökhan Öztürk