Hi everyone,

At my this post i will open a new area to my workings. From today on, i started to work about VDHL(1) language and FPGA(2) demo board. I took e lesson about VHDL language two years ago. We used Xilinx’s(3) program.  Then i refreshed my  knowledge about basics of digital computing. From now on  i will use Altera’s (4) “Altera Quartus II”.

If u have no idea about usage of Quartus 2 and Modelsim just watch this video (5). This guys  recounts well and it is gonna help you.

I designed this program to  make the basic logic operations.

library ieee;
use ieee.std_logic_1164.all;

entity example is
port ( A :  in std_logic_vector (1 downto 0);
B :  out std_logic_vector (3 downto 0));
end example;

architecture behavior of example is

begin
B(0) <= A(0) or A(1);
B(1) <= A(0) and A(1);
B(2) <= A(0) xor A(1);
B(3) <= A(0) nand A(1);

end behavior;

--ozturkgokhan.com

Let us examine the output of program.

Modelsim Output

As you see A(0)=0, A(1)=1. By the varying yellow line you can see results of outputs 
at second column.

B(0) is the output of or gate.   '0' or '1' equals 1.
B(1) is the output of and gate.  '0' and '1' equals 0
B(2) is the output of xor gate.  '0' xor'1' equals 1
B(3) is the output of nand gate. '0' nand '1' equals 1

Have a nice day,
Gökhan Öztürk

(1) https://en.wikipedia.org/wiki/VHDL
(2) https://en.wikipedia.org/wiki/Field-programmable_gate_array
(3) https://en.wikipedia.org/wiki/Xilinx
(4) https://en.wikipedia.org/wiki/Altera
(5) https://www.youtube.com/watch?v=9xr9ARUDxz4